1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to circuits and methods of operating circuits which allow for the storage of a signal value in operational, diagnostic and sleep modes.
2. Description of the Prior Art
It is known to provide a variety of different types of circuits for storing signal values. One common type of such circuits is the master slave latch arrangement. Another type of such circuit utilises cross-coupled sense amplifiers and is termed a sense amplifier flip-flop. Another known type of storage circuit is termed a hybrid latch flip-flop. It is also known to provide diagnostic capabilities in association with both these types of flip-flop by adding a scan cell capability whereby a signal value may be captured and then serially scanned out of the circuit for diagnostic purposes.
A further type of storage circuit is a clocked-scan flip-flop. A clocked-scan flip-flop provides diagnostic capabilities and has a number of advantages over the other types of flip flop which also provide diagnostic capabilities. In particular, a clocked scan flip-flop only requires two clock signals to provide its operational and diagnostic capabilities whereas the LSSD flip-flops require three clock signals. This additional clock signal overhead increases the circuit area consumed as well as having other disadvantages. Mux-D type flip-flops require only one clock signal but have the disadvantage of introducing a multiplexer delay into the processing path. Furthermore, clocked scan flip flops are more suited to high speed operation and generally provide lower power consumption than the Mux-D flip-flop designs.
In addition to providing operational and diagnostic modes it is known to also provide a data retention mode, also sometimes called a sleep mode. Such a mode of operation allows the stored signal values to be securely held in a small portion of the circuitry whilst the remainder of the circuitry is powered down for leakage reduction purposes. When power is resumed, the saved signal value is restored and operation continues. One approach to supporting data retention in this way is to add balloon latches to the flip-flops such that signal values can be transferred into the balloon latches which have their own power supply, and then the power supply removed from the remainder of the flip-flops. A disadvantage of this approach is that the balloon latches consume considerable additional circuit area.
It has been proposed for sense amplifier flip-flops and hybrid latch flip-flops which have associated scan cells operating in accordance with the level sensitive scan design methodology to reuse the scan cells for data retention during a power down mode of operation. Whilst this approach reduces the increase in circuit overhead associated with providing the data retention capability, it does require for control the three clock signals of the sense amplifier flip-flops or hybrid latch flip-flops with their known disadvantages in terms of speed, power consumption and other factors.